EP2C20256C7N - Altera Corporation - 1. Enhanced Configuration Devices (EPC4,

Product Specification

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Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet


Description:

The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks: a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made
up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete. Table 1–1 summarizes the features of Altera configuration devices and the amount of configuration space they hold.

Applications:
This chapter describes the EPC4, EPC8, and EPC16 enhanced configuration devices (EPC).
■ Single-chip configuration solution for Altera® ACEX® 1K, APEX™ 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria® GX, Cyclone®, Cyclone II, FLEX® 10K (including FLEX 10KE and FLEX 10KA), Mercury™, Stratix® II, and Stratix II GX devices
■ Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage
■ On-chip decompression feature almost doubles the effective configuration density
■ Standard flash die and a controller die combined into single stacked chip package
■ External flash interface supports parallel programming of flash and external
processor access to unused portions of memory
■ Flash memory block/sector protection capability via external flash interface
■ Supported in EPC16 and EPC4 devices
■ Page mode support for remote and local reconfiguration with up to eight
configurations for the entire system
■ Compatible with Stratix series Remote System Configuration feature
■ Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle
■ Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs
■ Pin-selectable 2-ms or 100-ms power-on reset (POR) time
■ Configuration clock supports programmable input source and frequency synthesis
■ Multiple configuration clock sources supported (internal oscillator and external clock input pin)
■ External clock source with frequencies up to 100 MHz
■ Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of 33, 50, and 66 MHz
■ Clock synthesis supported via user programmable divide counter
■ Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA® (UFBGA) packages
■ Vertical migration between all devices supported in the 100-pin PQFP package
■ Supply voltage of 3.3 V (core and I/O)
■ Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification
■ Supports ISP via Jam Standard Test and Programming Language (STAPL)
■ Supports JTAG boundary scan
■ nINIT_CONF pin allows private JTAG instruction to start FPGA configuration
■ Internal pull-up resistor on nINIT_CONF always enabled
■ User programmable weak internal pull-up resistors on nCS and OE pins
■ Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines
■ Standby mode with reduced power consumption
For more information about FPGA configuration schemes and advanced features, refer to the appropriate FPGA family chapter in the Configuration Handbook.


Specifications:

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