XC7S50-2CSGA324C Programmable IC Chips 7 Series FPGA 210 I/O 4075 Array Block

Product Specification

Programmable Ic XC7S50-2CSGA324C 7 Series FPGA 210 I/O 4075 Array Block CSGA-324

Specifications

Description

Xilinx® 7 series FPGAs comprise four FPGA families that address the complete range of system requirements,

ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity

bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications.

The 7 series FPGAs include:

• Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance.

Available in low-cost, very small form-factor packaging for smallest PCB footprint.

• Artix®-7 Family: Optimized for

low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total

bill of materials cost for high-throughput, cost-sensitive applications.

• Kintex®-7 Family: Optimized for best

price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.

• Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance.

Highest capability devices enabled by stacked silicon interconnect (SSI) technology. Built on a state-of-the-art,

high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable

an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3

TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative

to ASSPs 

Features

• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable

as distributed memory.

• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.

• High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.

• High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max. rates of 6.6 Gb/s

up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.

• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters

with on-chip thermal and supply sensors.

• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized

symmetric coefficient filtering.

• Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM)

blocks for high precision and low jitter.

• Quickly deploy embedded processing with MicroBlaze™ processor.

• Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.

• Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with

HMAC/SHA-256 authentication, and built-in SEU detection and correction.

• Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flipchip packaging offering easy migration between

family members in the same package. All packages available in Pb-free and selected packages in Pb option.

• Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process

technology and 0.9V core voltage option for even lower power.

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