ATF1504AS and ATF1504ASL Electrically-erasable Complex Programmable Logic Device

Product Specification

ATF1504AS and ATF1504ASL Electrically-erasable Complex Programmable Logic Device Integrated circuits IC Electronic components
 

Features:

High-density, High-performance, Electrically-erasable Complex Programmable Logic Device ̶ 64 Macrocells ̶ 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell ̶ 44, 84, 100 Pins ̶ 7.5ns Maximum Pin-to-pin Delay ̶ Registered Operation up to 125MHz ̶ Enhanced Routing Resources

In-System Programmability (ISP) via JTAG

Flexible Logic Macrocell ̶ D/T/Latch Configurable Flip-flops ̶ Global and Individual Register Control Signals ̶ Global and Individual Output Enable ̶ Programmable Output Slew Rate ̶ Programmable Output Open Collector Option ̶ Maximum Logic Utilization by Burying a Register with a COM Output

Advanced Power Management Features ̶ Automatic μA Standby for “L” Version ̶ Pin-controlled 1mA Standby Mode ̶ Programmable Pin-keeper Circuits on Inputs and I/Os ̶ Reduced-power Feature per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 44-lead and 84-lead PLCC; 44-lead and 100-lead TQFP

Advanced EE Technology ̶ 100% Tested ̶ Completely Reprogrammable ̶ 10,000 Program/Erase Cycles ̶ 20 Year Data Retention ̶ 2000V ESD Protection ̶ 200mA Latch-up Immunity

JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

PCI-compliant

3.3V or 5.0V I/O Pins

Security Fuse 

Green (Pb/Halide-free/RoHS Compliant) Package Options

Specification:

The Atmel ATF1504AS(L) is a high-performance, high-density Complex Programmable Logic Device (CPLD) which utilizes the Atmel proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI, and classic PLDs. The ATF1504AS(L) enhanced routing switch matrices increases usable gate count and the odds of successful pin-locked design modifications. The ATF1504AS(L) has up to 68 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset, or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 64 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term which goes to a regional bus. Cascade logic between macrocells in the ATF1504AS(L) allows fast, efficient generation of complex logic functions.

The ATF1504AS(L) contains four such logic chains; each capable of creating sum term logic with a fan-in of up to 40 product terms.

The ATF1504AS(L) macrocell, shown in Figure 1, is flexible enough to support highly-complex logic functions operating at high speed.

The macrocell consists of five sections:

Product Terms and Product Term Select Multiplexer

OR/XOR/CASCADE Logic

Flip-flop

Output Select and Enable

Logic Array Inputs

Programmable Pin-keeper Option for Inputs and I/Os

The ATF1504AS(L) offers the option of programming all input and I/O pins so the pin-keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high-level or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise.

The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.

 
Environmental & Export Classifications

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