3" Silicon Epitaxial Wafer Substrate Thickness 381±25µm / Resistivity <0.018Ωcm

Product Specification

3" Silicon Epitaxial Wafer Substrate Thickness 381±25µm / Resistivity <0.018Ωcm Epi Layer Thickness 20-25μm

Silicon epitaxial wafer is a layer of single crystal silicon deposited onto a single crystal silicon wafer(note: it is available to Grow a layer of poly crystalline Silicon layer on top of a highly doped Singly crystalline Silicon wafer, but it needs buffer layer (such as oxide or poly-Si) in between the bulk Si substrate and the top epitaxial layer)

The epitaxial layer can be doped, as it is deposited, to the precise doping concentration while continuing the substrate’s crystalline structure.

Epilayer resistivity: <1 ohm-cm up to 150 ohm-cm

Epilayer thickness: < 1 um up to 150 um

Structure: N/N+, N-/N/N+, N/P/N+, N/N+/P-, N/P/P+, P/P+, P-/P/P+.

Wafer Application: Digital, Linear, Power, MOS, BiCMOS Devices.

Our advantages at a glance

1. Advanced epitaxy growth equipment and test equipment.

2. Offer the highest quality with low defect density and good surface roughness.

3. Strong research team support and technology support for our customers

PAM-XIAMEN Epitaxial Wafer Services Specifications:

• Diameters: 50mm,75mm,100mm, 125mm, 150mm

• Wafer orientation: <100>, <111>, <110>

• EPI thickness: 4μm to 150μm

• Dopants: Arsenic, phosphorus, boron

• Typical resistivity ranges

• 0.05 – 1,200 ohm-cm

• 3000 – 5,000 ohm-cm (intrinsic layers)

3" Silicon Epitaxial Wafer Substrate Thickness 381 ± 25µm / Resistivity <0.018Ωcm, Epi Layer Thickness 20 - 25μm / Resistivity 7.5 - 10Ωcm

What is silicon epitaxial wafer?

Silicon epi wafers were first developed around 1966, and achieved commercial acceptance by the early 1980s.[5] Methods for growing the epitaxial layer on monocrystalline silicon or other wafers include: various types of chemical vapor deposition (CVD) classified as Atmospheric pressure CVD (APCVD) or metal organic chemical vapor deposition (MOCVD), as well as molecular beam epitaxy (MBE). Two "kerfless" methods (without abrasive sawing) for separating the epitaxial layer from the substrate are called "implant-cleave" and "stress liftoff". A method applicable when the epi-layer and substrate are the same material employs ion implantation to deposit a thin layer of crystal impurity atoms and resulting mechanical stress at the precise depth of the intended epi layer thickness. The induced localized stress provide a controlled path for crack propagation in the following cleavage step.[7] In the dry stress lift-off process applicable when the epi-layer and substrate are suitably different materials, a controlled crack is driven by a temperature change at the epi/wafer interface purely by the thermal stresses due to the mismatch in thermal expansion between the epi layer and substrate, without the necessity for any external mechanical force or tool to aid crack propagation. It was reported that this process yields single atomic plane cleavage, reducing the need for post lift-off polishing, and allowing multiple reuses of the substrate up to 10 times

Are You Looking for an Silicon Wafer?

PAM-XIAMEN is your go-to place for semiconductor wafers, including Silicon wafers, as we have been doing it for almost 30 years! Send us enquiry to learn more about the wafers that we offer and how we can help you with your next project. Our group team can give you technology support. send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com