UPSD3254A-40U6 Flash programmable ic Integrated circuit Chip 200A Current

Product Specification

UPSD3254A-40U6 Flash programmable ic Integrated circuit Chip 200A Current

UPSD3254A-40U6
Flash Programmable System Device with 8032 Microcontroller Core
 
FEATURES SUMMARY

■ The µPSD3200 Family combines a Flash PSD architecture with an 8032 microcontroller core The µPSD3200 Family of Flash PSDs features dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and one External Interrupt. As with other Flash PSD families, the µPSD3200 Family is also in-system programmable (ISP) via a JTAG ISP interface.

■ Large 8 KByte SRAM with battery back-up option

■ Dual bank Flash memories

– 128 KByte or 256 KByte main Flash memory

– 32 KByte secondary Flash memory

■ Content Security – Block access to Flash memory

■ Programmable Decode PLD for flexible address mapping of all memories.

■ High-speed clock standard 8032 core (12-cycle)

■ USB Interface (µPSD3234A-40U6 only)

■ I 2C interface for peripheral connections

■ Five Pulse Width Modulator (PWM) channels

■ Standalone Display Data Channel (DDC)

■ Six I/O ports with up to 50 I/O pins

■ 3000 gate PLD with 16 macrocells

■ Supervisor functions

■ In-System Programming (ISP) via JTAG

■ Zero-Power Technology

■ Single Supply Voltage – 4.5 to 5.5 V – 3.0 to 3.6 V

SUMMARY DESCRIPTION

■ Dual bank Flash memories

– Concurrent operation, read from memory one while erasing and writing the other. In-Application Programming (IAP) for remote updates

– Large 128 KByte or 256 KByte main Flash memory for application code, operating systems, or bit maps for graphic user interfaces

– Large 32 KByte secondary Flash memory divided in small sectors. Eliminate external EEPROM with software EEPROM emulation

– Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks

■ Large SRAM with battery back-up option

– 8 KByte SRAM for RTOS, high-level languages, communication buffers, and stacks

■ Programmable Decode PLD for flexible address mapping of all memories

– Place individual Flash and SRAM sectors on any address boundary

– Built-in page register breaks restrictive 8032 limit of 64 KByte address space

– Special register swaps Flash memory segments between 8032 “program” space and

“data” space for efficient In-Application Programming

■ High-speed clock standard 8032 core (12-cycle)

– 40 MHz operation at 5 V, 24 MHz at 3.3 V

– Two UARTs with independent baud rate, three 16-bit Timer/Counters and two External Interrupts

■ USB Interface (µPSD3234A-40U6 only)

– Supports USB 1.1 Slow Mode (1.5 Mbit/s)

– Control endpoint 0 and interrupt endpoints 1 and 2

■ I 2C interface for peripheral connections

– Capable of master or slave operation

■ Five Pulse Width Modulator (PWM) channels – Four 8-bit PWM units

■ Standalone Display Data Channel (DDC) – For use in monitor, projector, and TV applications – Compliant with VESA standards DDC1 and DDC2B – Eliminate external DDC PROM

■ Six I/O ports with up to 50 I/O pins

– Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG

– Eliminates need for external latches and logic

■ 3000 gate PLD with 16 macrocells – Create glue logic, state machines, delays, etc.

– Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software ...Free

■ Supervisor functions – Generates reset upon low voltage or watchdog time-out. Eliminate external supervisor device – Reset In pin

■ In-System Programming (ISP) via JTAG

– Program entire chip in 10

- 25 seconds with no involvement of 8032

– Allows efficient manufacturing, easy product testing, and Just-In-Time inventory

– Eliminate sockets and pre-programmed parts

– Program with FlashLINKTM cable and any PC

■ Content Security

– Programmable Security Bit blocks access of device programmers and readers

■ Zero-Power Technology

– Memories and PLD automatically reach standby current between input changes

■ Packages – 52-pin TQFP – 80-pin TQFP:

allows access to 8032 address/ data/control signals for connecting to external peripherals

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