DG441DJ Electronic IC Chips Monolithic , Quad SPST , CMOS Analog Switches

Product Specification

DG441, DG442

Monolithic, Quad SPST, CMOS Analog Switches

The DG441 and DG442 monolithic CMOS analog switches are drop-in replacements for the popular DG201A and DG202 series devices. They include four independent single pole single throw (SPST) analog switches, TTL and CMOS compatible digital inputs, and a voltage reference for logic thresholds.

These switches feature lower analog ON resistance (<85Ω) and faster switch time (t_ON < 250ns) compared to the DG201A and DG202. Charge injection has been reduced, simplifying sample and hold applications.

The improvements in the DG441 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 40V_P-P signals. Power supplies may be singleended from +5V to +34V, or split from ±5V to ±20V.

The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. The switches in the DG441 and DG442 are identical, differing only in the polarity of the selection logic.

Features

• ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 85Ω

• Low Power Consumption (P_D) . . . . . . . . . . . . . . . <1.6mW

• Fast Switching Action

  - t_ON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns

  - t_OFF (Max, DG441). . . . . . . . . . . . . . . . . . . . . . . . 120ns

• Low Charge Injection

• Upgrade from DG201A/DG202

• TTL, CMOS Compatible

• Single or Split Supply Operation

Applications

• Audio Switching

• Battery Operated Systems

• Data Acquisition

• Hi-Rel Systems

• Sample and Hold Circuits

• Communication Systems

• Automatic Test Equipment

Pinout

Functional Diagrams

Schematic Diagram (One Channel)

Absolute Maximum Ratings

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V

GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V

Digital Inputs, V_S, V_D (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First

Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA

Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40℃ to 85℃

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)

Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns

Thermal Information

Thermal Resistance (Typical, Note 2)                      θ_JA (℃/W)

    PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

    SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Maximum Junction Temperature (Plastic Packages) . . . . . . .150℃

Maximum Storage Temperature Range. . . . . . . . . . -65℃ to 150℃

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300℃

    (SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Signals on S_X, D_X or IN_X exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.

2. θ_JA is measured with the component mounted on an evaluation PC board in free air.

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