MT48LC32M8A2 Programmable IC Chips Synchronous DRAM 256Mb x4 x8 x16 SDRAM

Product Specification

MT48LC32M8A2 Programmable IC Chips Synchronous DRAM 256Mb x4 x8 x16 SDRAM

Synchronous DRAM

MT48LC64M4A2 – 16 Meg x 4 x 4 banks

MT48LC32M8A2 – 8 Meg x 8 x 4 banks

MT48LC16M16A2 – 4 Meg x 16 x 4 banks

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge, and auto refresh modes

• Self refresh mode

• 64ms, 8,192-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

Options                                                   Marking

• Configurations

  – 64 Meg x 4 (16 Meg x 4 x 4 banks)        64M4

  – 32 Meg x 8 (8 Meg x 8 x 4 banks)          32M8

  – 16 Meg x 16 (4 Meg x 16 x 4 banks)      16M16

• Write recovery (^t WR)

  – ^t WR = “2 CLK”¹                                      A2

• Plastic package – OCPL²

  – 54-pin TSOP II OCPL² (400 mil)             TG

     (standard)

  – 54-pin TSOP II OCPL2 (400 mil)             P

     Pb-free

  – 60-ball FBGA (x4, x8) (8mm x 16mm)      FB

  – 60-ball FBGA (x4, x8) Pb-free                 BB

     (8mm x 16mm)

  – 54-ball VFBGA (x16) (8mm x 14 mm)      FG 

  – 54-ball VFBGA (x16) Pb-free                  BG

     (8mm x 14 mm)  

• Timing (cycle time)

  – 6.0ns @ CL = 3 (x8, x16 only)                -6A

  – 7.5ns @ CL = 3 (PC133)                        -75

  – 7.5ns @ CL = 2 (PC133)                        -7E

• Self refresh

  – Standard                                                None

  – Low power                                              L³

• Operating temperature range

  – Commercial (0°C to +70°C)                   None

  – Industrial (–40°C to +85°C)                    IT

• Design revision :                                       D

Notes: 1. Refer to Micron technical note: TN-48-05.

           2. Off-center parting line.

           3. Contact Micron for availability.

General Description

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0–A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.

The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

64 Meg x 4 SDRAM Functional Block Diagram

32 Meg x 8 SDRAM Functional Block Diagram

16 Meg x 16 SDRAM Functional Block Diagram